1. Field of the Invention
The present invention generally relates to systems and methods for discovering defects on a wafer, which are particularly useful for setting up a wafer inspection process.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Inspection processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspection has always been an important part of fabricating semiconductor devices such as ICs. However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail.
Many different types of inspection systems have adjustable output acquisition (e.g., data, signal, and/or image acquisition) and sensitivity (or defect detection) parameters such that different parameters can be used to detect different defects or avoid sources of unwanted (nuisance) events. Although an inspection system that has adjustable output acquisition and sensitivity parameters provides significant advantages to a semiconductor, device manufacturer, these inspection systems are essentially useless if the incorrect output acquisition and sensitivity parameters are used for an inspection process. In addition, since the defects, process conditions, and noise on wafers may vary dramatically (and since the characteristics of the wafers themselves may vary dramatically), the best output acquisition and sensitivity parameters for detecting defects on a particular wafer may be difficult, if not impossible, to predict. Therefore, although using the correct output acquisition and sensitivity parameters will have a dramatic effect on the results of inspection, it is conceivable that many inspection processes are currently being performed with incorrect or non-optimized output acquisition and sensitivity parameters.
An optimal inspection recipe for a semiconductor layer should detect as many defects of interest (DOIs) as possible while maintaining a substantially low nuisance rate. Optimizing an inspection recipe generally involves tuning the parameters used in the recipe until the optimal result is achieved. The set of parameters to be tuned thus depends on the detection algorithm used.
One best known method for recipe optimization is to run a substantially “hot” inspection thereby increasing the likelihood of detecting DOI but at the expense of substantially high nuisance rates. The user then takes this hot lot and the wafer to a scanning electron microscope (SEM) for review. The user reviews the defects using the SEM and classifies the defects as real, nuisance, or DOI. Once enough of each type of defect is classified, the user attempts to set the correct defect detection parameter values in order to create a recipe that will detect enough of the DOI and have as few as possible of the nuisance defects detected. The more defects that are classified, the better the recipe can be. The user may then re-inspect the wafer using the new recipe and use the SEM to review the defects detected on the wafer using the new recipe. In this manner, re-inspection and defect review may be performed in an iterative manner until the user determines that satisfactory defect detection can be achieved by the recipe based on defect review results.
One problem with such methods is that it takes significant time to SEM review a single defect. In addition, the need for multiple trips between the inspection system and the SEM adds significant time to the recipe setup. The user would ideally like to review the smallest number of defects possible that would still produce an accurate recipe and be able to do this in one trip to the SEM.
Accordingly, it would be advantageous to develop systems and methods for discovering defects on a wafer that do not have one or more of the disadvantages described above.